Design of low latency asynchronous arbiter based on standard cell library

In this paper, a low-latency asynchronous arbiter based on standard cell library was proposed. The circuit which implemented library, could be synthesized by mainstream EDA tools and suitable for being part of large-scale digital designs. With the employment parallel processing techniques, Quick Request Forward Acknowledgement Release, were able to reduce release time shortening long feedback delay, proposed provide low latency. Post-layout simulations showed that cycle 7.3-40% better than existing arbiters in terms latency simple communication model 35.26-81.84% complex model. addition, advantage became distinct as N increased.